The VLTI Control System Current Development
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Contents

• VLTI Fast Link
• Principle of Operation
• In-House Development
• Fringe Control Loop Prototype
• Proto Type Equipment

The VLTI Fast Link

The OPD Controller is the subsystem acting as a bridge between the FSU LCU and every DL LCU. The FSU LCU computes every 250 microsec (4 kHz) a set of OPD error signals. Each OPD error signal results from the processing of the fringe pattern generated by the interference of an incoming light beam with the reference one (a pair of beams identifies a baseline).

The OPDC LCU is then needed to accomplish the following tasks:

• receive the set of OPD messages from the FSU LCU
• check the validation flags of each OPD message
• filter the OPD values measured by the FSU at 4 kHz
• receive the current position of each DL at 1 kHz
• apply specific control algorithms
• decide the optimal motion of the DLs array
• distribute the appropriate control signal to each DL LCU at 1kHz minimum

After surveying the products that are currently available on the market for high-speed data communication, the reflective memory network technology has been selected as the most suitable solution, which satisfies the Fast Link performance requirements and operational constraints.

Hardware selected: VMIC VMIVME 5576 Reflective Memory Board

Principle of Operation

A reflective memory network is composed by a reflective memory board installed in each interconnected node and optical fibre cable between every two adjacent nodes. Whenever a processor on any backplane in the network writes data into its local reflective memory board, that data is simultaneously stored in that onboard memory and broadcast to all the other similar remote boards. The broadcast data are received and stored in the corresponding location on each of the other reflective memory boards in the network. Within a few microseconds each CPU has an up-to-date local copy of shared memory. Thus, although the memory is physically located and accessed in the local backplane, the CPUs have the illusion that they are using a common memory area.

Since the CPUs in a reflective memory network do not have to share the access to a common physical memory area, they can each access the data stored in their reflective memory with minimal access time. Because the broadcasts are done strictly with the hardware, they can be accomplished very quickly. This makes reflective memory useful for real-time distributed multiprocessing systems, in which data latency must be kept very low. In fact, reflective memory can reduce latency to a few microseconds.

In-house Development

VLTI Fast Link Network

The Fringe Control Loop Prototype

The prototype set-up is shown below.

Prototype Equipment

• The light beam is generated by a laser head
• The FSU is simulated by the Zygo AXIOM 2/20 laser interferometer
• The DL is simulated by the Anorad Model 5 translation stage
• The Cat's Eye is made of a Matsukov photographic objective
• The piezo element mounted in the cat's eye is a Queensgate DPT-C L 70
• The LCU control hardware is realized with VLT standard VME boards
• The LCU control software is based on VLTSW

Send comments to <mverola@eso.org> Last update: Apr 27, 1998