Hardware Setup and Filter Settings

Preamp-Box

For Channels 0 and 1 (MIT) the last stage load is a 3.3KR resistor, all the rest is standard.

Videoboard

Offset settings : -10 to 0 V for MIT, -5 to 0 V for EEV

High Gain setting

The high gain settings are only used at 255 and 50 Kpx Mode

0.6 e-/ADU

  EEV MIT
Op amp Gain 1 Preamp Box 2.25 (standard) set to 1 2.25 (standard) set to 1
Op amp Gain 2 Video Board 19 (R1=649R, R2=36 R) set to 1 6.4 (R1=649R, R2=120 R) set to 1

Low Gain setting

The low gain settings are only used at 625 Kpx Mode

1.6 e-/ADU

  EEV MIT
Op amp Gain 1 Preamp Box 3 (standard) set to 2 3 (standard) set to 2
Op amp Gain 2 Video Board 6.4 (R1=649R, R2=120 R) set to 0 2.5 (R1=649R, R2=430 R) set to 0

Filter settings

Speed EEV MIT
  Filter Value Cap Filter Value Cap
50 3 t = 3000 ns 2nF 3 t = 3000 ns 2nF
225 1 t = 500 ns 220pF 1 t = 500 ns 220pF
625 0 t = 150 ns 100pF 0 t = 150 ns 100pF

Filter 2 is not used...

Clockdriver board

Simm DAC EEV MIT
Phase Output Resistor Phase Output Resistor
0 BRD_CLKDRV0 CLKDRV_DAC0 SWL 50 R SWA 50 R
1 BRD_CLKDRV0 CLKDRV_DAC1 SWR 50 R SWB 50 R
2 BRD_CLKDRV0 CLKDRV_DAC2 RF3 50 R S3 50 R
3 BRD_CLKDRV0 CLKDRV_DAC3 RF2L 50 R S2A 50 R
4 BRD_CLKDRV0 CLKDRV_DAC4 RF1L 50 R S1A 50 R
5 BRD_CLKDRV0 CLKDRV_DAC5 RF2R 50 R S2B 50 R
6 BRD_CLKDRV0 CLKDRV_DAC6 RF1R 50 R S1B 50 R
7 BRD_CLKDRV0 CLKDRV_DAC7 DG 50 R empty 50 R
8 BRD_CLKDRV0 CLKDRV_DAC8 IF1 10 R P1 10 R
9 BRD_CLKDRV0 CLKDRV_DAC9 IF2 10 R P2 10 R
10 BRD_CLKDRV0 CLKDRV_DAC10 IF3 10 R P3 10 R
11 BRD_CLKDRV0 CLKDRV_DAC11 empty 10 R empty 10 R
12 BRD_CLKDRV0 CLKDRV_DAC12 FRL 50 R RGA 50 R
13 BRD_CLKDRV0 CLKDRV_DAC13 FRR 50 R RGB 50 R

Communication Board

Default, no modifications.

Biasboard

Default, no modifications.

Power Supplies

Default,
+ 15 V, 4 A;
- 15 V, 4 A;
+ 30 V, 1 A;
+ 24 V, 5 A;
+ 5 V, 8 A.

DSP Board ( 40 Mhz )

Default, no modifications.

Benner Board

Default, no modifications.

Sparc Computer

Default, no modifications.


Voltage Setup - Global Voltage Definition Table Micro Sequences

This table defines the voltages which will be applied to peripherals at initialisation time. It also defines the high and low limits which may be set for these voltages.

Biasboard 0 for the EEV-CCD 44 in the Mosaic

Anabias voltages are in 0.001 Volts.
BRD_ID     PERIPH_ID LOW HIGH INIT_VAL USED FOR
Connector P0 - A :
BRD_ANABIAS0 ANB_PRESET_VOLT_A - 3500 - 1000 - 3500 OG1R
BRD_ANABIAS0 ANB_PRESET_VOLT_B - 2500 - 1000 - 2500 OG2R
BRD_ANABIAS0 ANB_PRESET_VOLT_C 2000 25000 23000 ODR
BRD_ANABIAS0 ANB_PRESET_VOLT_D 2000 15000 12000 RDR
BRD_ANABIAS0 ANB_PRESET_VOLT_E 2000 25000 24000 JDR
BRD_ANABIAS0 ANB_PRESET_VOLT_F 0 0 0 not used
BRD_ANABIAS0 ANB_PRESET_VOLT_G 0 0 0 not used
BRD_ANABIAS0 ANB_PRESET_VOLT_H 0 0 0 not used
Connector P0 - B :
BRD_ANABIAS0 ANB_PRESET_VOLT_I - 3500 - 1000 - 3500 OD1L
BRD_ANABIAS0 ANB_PRESET_VOLT_J - 2500 - 1000 - 2500 OG2L
BRD_ANABIAS0 ANB_PRESET_VOLT_K 2000 25000 23000 ODL
BRD_ANABIAS0 ANB_PRESET_VOLT_L 2000 15000 12000 RDL
BRD_ANABIAS0 ANB_PRESET_VOLT_M 2000 25000 24000 JDL
BRD_ANABIAS0 ANB_PRESET_VOLT_N 0 0 0 not used
BRD_ANABIAS0 ANB_PRESET_VOLT_O 2000 19000 18000 DDLR
BRD_ANABIAS0 ANB_PRESET_VOLT_P 0 0 0 not used

Biasboard 1 for the MIT / LL CCID in the Mosaic

Anabias voltages are in 0.001 Volts.

BRD_ID     PERIPH_ID LOW HIGH INIT_VAL USED FOR
Connector P0 - C :
BRD_ANABIAS1 ANB_PRESET_VOLT_A 5000 20000 19000 OD-A
BRD_ANABIAS1 ANB_PRESET_VOLT_B 0 0 0 OG-A
BRD_ANABIAS1 ANB_PRESET_VOLT_C 5000 15000 12500 RD-A
BRD_ANABIAS1 ANB_PRESET_VOLT_D 5000 12000 10000 SCP-A
BRD_ANABIAS1 ANB_PRESET_VOLT_E 0 0 0 not used
BRD_ANABIAS1 ANB_PRESET_VOLT_F 0 0 0 not used
BRD_ANABIAS1 ANB_PRESET_VOLT_G 0 0 0 not used
BRD_ANABIAS1 ANB_PRESET_VOLT_H 0 0 0 not used
Connector P0 - D :
BRD_ANABIAS1 ANB_PRESET_VOLT_I 5000 20000 19000 OD-B
BRD_ANABIAS1 ANB_PRESET_VOLT_J 0 0 0 OG-B
BRD_ANABIAS1 ANB_PRESET_VOLT_K 5000 15000 12500 RD-B
BRD_ANABIAS1 ANB_PRESET_VOLT_L 5000 12000 10000 SCP-B
BRD_ANABIAS1 ANB_PRESET_VOLT_M 0 0 0 not used
BRD_ANABIAS1 ANB_PRESET_VOLT_N 0 0 0 not used
BRD_ANABIAS1 ANB_PRESET_VOLT_O 0 0 0 not used
BRD_ANABIAS1 ANB_PRESET_VOLT_P 0 0 0 not used
The anabias board also has an opto isolated peripheral :
BRD_ANABIAS1 ANB_OPTOOUT 0 32767 255  

Clockdriverboard 0 for the EEV-CCD 44 in the Mosaic

Clock driver rail voltages are in 0.001 Volts.

BRD_ID     PERIPH_ID LOW HIGH INIT_VAL USED FOR
Connector P0 - A :
BRD_CLKDRV0 CLKDRV_DAC0_LO - 5000 - 5000 - 5000 SWL
BRD_CLKDRV0 CLKDRV_DAC0_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC1_LO - 5000 - 5000 - 5000 SWR
BRD_CLKDRV0 CLKDRV_DAC1_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC2_LO - 5000 - 5000 - 5000 RF3
BRD_CLKDRV0 CLKDRV_DAC2_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC3_LO - 5000 - 5000 - 5000 RF2L
BRD_CLKDRV0 CLKDRV_DAC3_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC4_LO - 5000 - 5000 - 5000 RF1L
BRD_CLKDRV0 CLKDRV_DAC4_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC5_LO - 5000 - 5000 - 5000 RF2R
BRD_CLKDRV0 CLKDRV_DAC5_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC6_LO - 5000 - 5000 - 5000 RF1R
BRD_CLKDRV0 CLKDRV_DAC6_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC7_LO - 6000 - 6000 - 6000 DG
BRD_CLKDRV0 CLKDRV_DAC7_HI 6000 6000 6000
Connector P0 - B :
BRD_CLKDRV0 CLKDRV_DAC8_LO - 12000 - 4000 - 8000 IF1
BRD_CLKDRV0 CLKDRV_DAC8_HI - 2000 3000 2000
BRD_CLKDRV0 CLKDRV_DAC9_LO - 12000 - 4000 - 8000 IF2
BRD_CLKDRV0 CLKDRV_DAC9_HI - 2000 3000 2000
BRD_CLKDRV0 CLKDRV_DAC10_LO - 12000 - 4000 - 8000 IF3
BRD_CLKDRV0 CLKDRV_DAC10_HI - 2000 3000 2000
BRD_CLKDRV0 CLKDRV_DAC11_LO 0 0 0 empty
BRD_CLKDRV0 CLKDRV_DAC11_HI
BRD_CLKDRV0 CLKDRV_DAC12_LO - 6000 - 4000 - 6000 FRL
BRD_CLKDRV0 CLKDRV_DAC12_HI 6000 8000 6000
BRD_CLKDRV0 CLKDRV_DAC13_LO - 6000 - 4000 - 6000 FRR
BRD_CLKDRV0 CLKDRV_DAC13_HI 6000 8000 6000

Clockdriverboard 1 for the MIT / LL CCID in the Mosaic

Clock driver rail voltages are in 0.001 Volts.

BRD_ID     PERIPH_ID LOW HIGH INIT_VAL USED FOR
Connector P0 - C :
BRD_CLKDRV1 CLKDRV_DAC0_LO - 5000 - 5000 - 5000 SWA
BRD_CLKDRV1 CLKDRV_DAC0_HI 5000 5000 5000
BRD_CLKDRV1 CLKDRV_DAC1_LO - 5000 - 5000 - 5000 SWB
BRD_CLKDRV1 CLKDRV_DAC1_HI 5000 5000 5000
BRD_CLKDRV1 CLKDRV_DAC2_LO - 3000 - 3000 - 3000 S3
BRD_CLKDRV1 CLKDRV_DAC2_HI 6000 6000 6000
BRD_CLKDRV1 CLKDRV_DAC3_LO - 3000 - 3000 - 3000 S2A
BRD_CLKDRV1 CLKDRV_DAC3_HI 6000 6000 6000
BRD_CLKDRV1 CLKDRV_DAC4_LO - 3000 - 3000 - 3000 S1A
BRD_CLKDRV1 CLKDRV_DAC4_HI 6000 6000 6000
BRD_CLKDRV1 CLKDRV_DAC5_LO - 3000 - 3000 - 3000 S2B
BRD_CLKDRV1 CLKDRV_DAC5_HI 6000 6000 6000
BRD_CLKDRV1 CLKDRV_DAC6_LO - 3000 - 3000 - 3000 S1B
BRD_CLKDRV1 CLKDRV_DAC6_HI 6000 6000 6000
BRD_CLKDRV1 CLKDRV_DAC7_LO 0 0 0 empty
BRD_CLKDRV1 CLKDRV_DAC7_HI
Connector P0 - D :
BRD_CLKDRV1 CLKDRV_DAC8_LO - 8000 - 6000 - 6000 P1
BRD_CLKDRV1 CLKDRV_DAC8_HI 2000 2000 2000
BRD_CLKDRV1 CLKDRV_DAC9_LO - 8000 - 6000 - 6000 P2
BRD_CLKDRV1 CLKDRV_DAC9_HI 2000 2000 2000
BRD_CLKDRV1 CLKDRV_DAC10_LO - 8000 - 6000 - 6000 P3
BRD_CLKDRV1 CLKDRV_DAC10_HI 2000 2000 2000
BRD_CLKDRV1 CLKDRV_DAC11_LO 0 0 0 empty
BRD_CLKDRV1 CLKDRV_DAC11_HI
BRD_CLKDRV1 CLKDRV_DAC12_LO 0 0 0 RGA
BRD_CLKDRV1 CLKDRV_DAC12_HI 10000 12000 10000
BRD_CLKDRV1 CLKDRV_DAC13_LO 0 0 0 RGB
BRD_CLKDRV1 CLKDRV_DAC13_HI 10000 12000 10000