AQ sixteen channel

AQ sixteen channel (CS-P-1916- revsision C)

Features

• Sixteen of ADC's (333 KHz)
• VME compatible
• Double Euro size module
• True differential analog inputs
• Low noise design
• Delay for ADC convert signal - software controlled up to 3 us by 50 ns steps
• AQ modules can be cascaded
• Monitor of ADC-inputs and the convert signal via front panel LEMO's
• On board ADC-emulator

General Description

Each acquisition module will be selected automatically as a master module by the slot-ID (if it is set). It then generates a header code, corresponding to the header, which is set in the status register one. Header word followed by the ADC data will put out over the GIGA bus. If the module is not a master, it just puts out the ADC data to the synchronous GIGA bus.

To be synchron to another AQ, there is a signal called "Moving bit". Each module sends his data if the "MovingBitIn" signal is low (low active), after them it generates for the next Aq module the signal "MovingBitOut" and so on...

The acquisition module has sixteen channels and contains minimum digital logic, so those low-level analog signals are not disturbed by digital noise. The differential analog input signals of each channel are input to a discrete buildup amplifier followed by a low pass filters in front of the ADCs. A conversion command triggers the ADCs, which has a convert time of 3 usec and the data are immediately transferred to the output registers. Each two output register (16 bit) send their data at the same time to the GIGA bus (32 bit width) on the P2 connector of backplane. The convert signal has a programmable delay from 0 to 3 sec in steps of 200 nsec.

AQ sixteen channel (CS-P-1916- revsision F)

Features

• Sixteen of ADC's (500 KHz)
• Offset elimination circuit of video input signal
• VME interface
• Double Euro size module
• True differential analog inputs
• Low noise design
• Delay for ADC convert signal - software controlled up to 3 us by 50 ns steps
• AQ modules can be cascaded
• Monitor of ADC-inputs and the convert signal via front panel

General Description

Each acquisition module will be selected automatically as a master module by the slot-ID (if it is set). It then generates a header code, corresponding to the header, which is set in the status register one. Header word followed by the ADC data will put out over the GIGA bus. If the module is not a master, it just puts out the ADC data to the synchronous GIGA bus.

To be synchron to another AQ, there is a signal called "Moving bit". Each module sends his data if the "MovingBitIn" signal is low (low active), after them it generates for the next Aq module the signal "MovingBitOut" and so on...

The acquisition module has sixteen channels and contains minimum digital logic, so those low-level analog signals are not disturbed by digital noise. The differential analog input signals of each channel are input to a discrete buildup amplifier followed by a low pass filters in front of the ADCs. A conversion command triggers the ADCs, which has a convert time of 3 usec and the data are immediately transferred to the output registers. Each two output register (16 bit) send their data at the same time to the GIGA bus (32 bit width) on the P2 connector of backplane. The convert signal has a programmable delay from 0 to 3 sec in steps of 200 nsec.