IRACE, FRONT-END BACK PLANE

• Integration of System TTL master clock
• VME bus compatible (P1 and P2)
• Two AQ modules can plug in
• Slot ID are adjustable on backplane ((JPx3..JPx0)
• Master/Slave properties can be set on backplane (JPx5)
• Data bus and control signals can be terminated on backplane
• Stripline are imbedded within the PCB groung layers
• A stripline exhibits better signal integrity because the reference planes shield the conductor from damaging EMI fields.