VLT Control Model

Overview

The VLT Control Model has been designed to cater for the need of a HW/SW environment for integration, tests, measure of performances etc. It is used to validate Software Releases before they are sent to Paranal and to reproduce problems in Garching, in order to support the Paranal Observatory. It consists of a copy of the workstations and LCUs integrated for one of the VLT Telescopes at Paranal, including all the networks and routers in between. The LCUs have interface cards and have a variable amount of hardware connected when considered interesting to test (limited simulation).

Control Model Room

Control Model LCUs Racks

Purposes:

Model of control system and control room at Paranal.
Validation of Software Releases
Integration tests for subsystems and instruments.
Parallel testing of same software in Garching and at test sites.
TCS software simulation environment.
Test performances with Paranal network configuration.
Test user interface concepts.
Test HOS concepts, like Access and Configuration Control.
Test integration with DMD products: Catalogues, Archive, Scheduler, Phase II

Present VLT Control Model Architecture

Workstation's Configuration

VLT Machines

Name	Model	Op. System	VLT Sw	Disk	Memory
wt0tcs	HP 5600	HP-UX 11.0	CCSLite	9Gb+9Gb	512Mb
wg0acc	HP C110	HP-UX 10.20	FullCCS	4Gb+4Gb	128Mb
wa0exp	HP C110	HP-UX 10.20	FullCCS (obsolete version)	9Gb+18Gb	512Mb
wt0exp	HP J2240	HP-UX 11.0	CCSLite (obsolete version)
wtcdc	SUN sparc	SunOS 2.5.1	CCSlite	2Gb+4Gb	128Mb
wi01		HP-UX 10.20	FullCCS
wi02		HP-UX 11.0	CCSLite
wt0lux	PC	Linux	CCSLite

DMD Machines

Name	Model	Op. System	VLT Sw	Disk	Memory
wu0pl	HP C200	HP-UX 10.20	NOCCS	9Gb+18Gb	512Mb
wu0dhs	HP C200	HP-UX 10.20	NOCCS	9Gb+18Gb	256Mb
wu0oh	HP C200	HP-UX 10.20	CCSlite	9Gb+18Gb	256Mb
wg0off	HP 715/50	HP-UX 10.20	NOCCS	4Gb	32Mb
wg0arc	HP 715/50	HP-UX 10.20	NOCCS	4Gb	32Mb

LCU's Configuration

lt0alt/lt0az

1 VLT-standard MVME167 CPU board from Motorola

3 digital I/O board AVME948X from ACROMAG

1 analog I/O board VIVME3111 from VMIC

1 TIM time board connected to the time distribution system

1 Heidenhain IK320 encoder interface boards

Both boards are connected to a MTR 24...60/5 Motor that simulates the real telescope axis motor

lt0hb

1 VLT-standard MVME167 CPU board from Motorola

1 VLT-standard Digital I/O board AVME948X from ACROMAG

1 VLT-standard Serial I/F board ISER8 from ISD with eight serial RS232/V.24 channels

lt0enc

1 VLT-standard MVME167 CPU board from Motorola

1 VLT-standard Digital I/O board AVME948X from ACROMAG

1 analog I/O board VIVME3111 from VMIC

1 VLT-standard Serial I/F board ISER8 from ISD, which contains eight serial RS232/V.24 channel

lt0m1m3

1 standard Motorola MVME 167 CPU

lt0m2

2 VLT-standard MVME167 CPU board from Motorola

1 TIM time board connected to the time distribution system

1 MAC4 INC motion controller from MACCON

1 ESO VME4SA Servo amplifier board

lt0adc

1 standard Motorola MVME 2604 with PPC CPU

1 ESO TIM time board connected to the time distribution system

1 digital I/O boards AVME948X from ACROMAG

2 analog I/O board VIVME3111 from VMIC

1 MAC4 INC motion controller from MACCON

1 ESO VME4SA Servo amplifier board

lt0agc

1 standard Motorola MVME 2604 with PPC CPU

1 TIM time board connected to the time distribution system

1 INMOS BO16 Transputer Interface board

1 ESO Transputer Link Interface board

1 digital I/O boards AVME948X from ACROMAG

The LCU is connected to a complete CCD ACE Box

lt0iac

1 standard Motorola MVME 167 CPU

1 TIM time board connected to the time distribution system

1 INMOS BO16 Transputer Interface board

1 ESO Transputer Link Interface board

The LCU is connected to a complete CCD ACE Box

VLT Control Model

Overview

Purposes:

Present VLT Control Model Architecture

Workstation's Configuration

VLT Machines

DMD Machines

LCU's Configuration

lt0alt/lt0az

lt0hb

lt0enc

lt0m1m3

lt0m2

lt0adc

lt0agc

lt0iac

Tests on new releases:

YEAR 2000 Compliance Tests Report