General Description of IRACE

IRACE version 1 Detector Front-End

DFE consists of at least five boards, standard double Euro card size, placed in a VME size crate. Sequencer as well as clock/bias driver and ADC modules can be cascaded, to adapt to individual system requirements. SEQUENCER CLDC (Clock/Bias driver) AQ (ADC’s and Preamplifier’s) GIGA (High Speed Data Link) TIF (Transputer Fiber optic Link Interface) Detector Back-End DBE consists of at least three modules in standard double Euro card size, placed in a VME size crate. GIGA and TIF are the same modules type as on the front-end side TIF (Transputer Fiber optic Link Interface) GIGA (High Speed Data Link) DMA-Interface (Interface Gigalink Bus to NC DMA controller)

General Description DMA-IF interfaces the Giga Bus to the SUN Sbus DMA controller SCD 60. The 32Bit Giga Bus enters on P2 the DMA-IF. In an Altera PLD all logic for header recognition is done and the 32Bits of Giga Bus are de-multiplexed to the 16Bit size of the SUN Sbus DMA controller. From Altera, the data are feed into a FIFO. The FIFO output runs into a voltage level conversion circuit with the appropriate signals for SCD20 (TTL) or SCD60 (LVTTL). The appropriate driver circuits are installed at module assembly. The module than can only be used for either SCD20 or SCD60!.

IRACE version 2 Detector Front-End

DFE consists of at least five boards, standard double Euro card size, placed in a VME size crate. Sequencer as well as clock/bias driver and ADC modules can be cascaded, to adapt to individual system requirements. SEQUENCER CLDC (Clock/Bias driver) AQ (ADC’s and Preamplifier’s) GIGA (High Speed Data Link) TIF (Transputer Fiber optic Link Interface) Detector Back-End DBE consists of at least three modules in standard double Euro card size, placed in a VME size crate. GIGA and TIF are the same modules type as on the front-end side TIF (Transputer Fiber optic Link Interface) GIGA (High Speed Data Link) DMA-Interface (Interface Gigalink Bus to NC DMA controller)

General Description DMA-IF interfaces the Giga Bus to the SUN Sbus DMA controller SCD 60. The 32Bit Giga Bus enters on P2 the DMA-IF. In an Altera PLD all logic for header recognition is done and the 32Bits of Giga Bus are de-multiplexed to the 16Bit size of the SUN Sbus DMA controller. From Altera, the data are feed into a FIFO. The FIFO output runs into a voltage level conversion circuit with the appropriate signals for SCD20 (TTL) or SCD60 (LVTTL). The appropriate driver circuits are installed at module assembly. The module than can only be used for either SCD20 or SCD60!.

IRACE version 3 Detector Front-End

DFE consists of at least five boards, standard double Euro card size, placed in a VME size crate. Sequencer as well as clock/bias driver and ADC modules can be cascaded, to adapt to individual system requirements. SEQUENCER CLDC (Clock/Bias driver) AQ (ADC’s and Preamplifier’s) GIGA (High Speed Data Link) Detector Back-End DBE consists of at least three modules in standard double Euro card size, placed in a VME size crate. GIGA and TIF are the same modules type as on the front-end side GIGA (High Speed Data Link) DMA-Interface (Interface Gigalink Bus to NC DMA controller)

General Description DMA-IF interfaces the Giga Bus to the SUN Sbus DMA controller SCD 60. The 32Bit Giga Bus enters on P2 the DMA-IF. In an Altera PLD all logic for header recognition is done and the 32Bits of Giga Bus are de-multiplexed to the 16Bit size of the SUN Sbus DMA controller. From Altera, the data are feed into a FIFO. The FIFO output runs into a voltage level conversion circuit with the appropriate signals for SCD20 (TTL) or SCD60 (LVTTL). The appropriate driver circuits are installed at module assembly. The module than can only be used for either SCD20 or SCD60!.